CALL FOR PAPERS
             IEEE Journal on Selected Areas in Communications 

            HIGH-PERFORMANCE OPTICAL/ELECTRONIC SWITCHES/ROUTERS
                          FOR HIGH-SPEED INTERNET

   The Internet has been growing at an exponential rate. Driving this
   growth is the fact that the Internet has moved from a convenience to a
   mission-critical platform for conducting and succeeding in business.
   For example, current estimates predict that Internet backbone traffic
   will increase by at least 300% per year until 2003, and UUNet, the
   world's largest ISP, says it expects traffic on its regional trunks to
   be in the 1-10 petabit range over the next four to five years. As a
   result, there is a great demand for Gigabit/Terabit routers and
   switches (IP routers, ATM switches, Ethernet switches, Optical circuit
   switches, Burst switches) that knit together the constituent networks
   of the global Internet, creating the illusion of a unified whole.
   These switches/routers must not only have an aggregate capacity of
   Gigabits/Terabits per second coupled with forwarding rates of billions
   of packets per second, but they must also deal with nontrivial issues
   such as scheduling support for differentiated services, a wide variety
   of interface types, scalability in terms of capacity and port density,
   and backward compatibility with a wide range of packet formats and
   routing protocols.

   The academic and commercial trend towards the design of these
   routers/switches is based on whether these routers/switches are for
   circuit/burst switching or for packet switching. Packet switches are
   typically designed using electronic technology, and are targeted as an
   Internet edge router or a MAN/LAN switch. On the other hand,
   circuit/burst switches/routers are typically designed using optical
   technology, and are targeted as an Internet core router. At the same
   time, the push for integrated IP over WDM has given new and strong
   incentives for other classes of switches/routers such as optical
   packet/burst switching and hybrid optical electronic switches/routers.
   Additionally, future prospects for optical packet switches is an area
   of intense research.

   The scope of this issue is to address the research and development of
   these various classes of routers: optical or hybrid
   circuit/burst/packet core switches/routers, and electronic packet edge
   routers that feed the core, as well as the different classes of
   network infrastructures. In particular, we are interested in papers
   dealing with state-of-the art design and analysis of high-performance
   packet/circuit/burst switches and routers, and their influence on the
   operation and functionality of network infrastructures. In this
   context, topics include:

     * High-performance electronic or hybrid packet switches
     * Optical burst/packet switches
     * Optical circuit switches
     * Circuit switched network infrastructures
     * Packet switched network infrastructures
     * Virtual concatenation and burst switching
     * Performance evaluation and models
     * Quality-of-service provisioning
     * Traffic management and control
     * Experimental test-beds and results
     * MPLS and aggregate traffic scheduling
     * Differentiated services
     * Multicast support
     * Congestion management and control
     * Look-up and classification algorithms
     * Multistage and single stage switching fabrics
     * Programmable routers
     * Open and standard fabric interfaces

   Original, unpublished contributions and invited articles will be
   considered for the issue. The paper should follow the IEEE J-SAC
   manuscript format described in the Information for Authors, and no
   longer than 20 double-spaced pages, excluding illustrations and
   graphs.

   Authors wishing to submit papers, should send an electronic version
   (postscript or PDF files ONLY) of their complete manuscript, as well
   as a cover letter (text format) which contains the paper title,
   authors with affiliations, and a 200-word abstract to Mounir Hamdi by
   August 1, 2002. The following timetable will apply:

   Submission Deadline:     AUGUST 1, 2002
   Acceptance notification: December 1, 2002
   Final manuscript due:    January 1, 2003
   Publication of issue:    2nd Quarter 2003

   Guest Editors:
   Mounir Hamdi, Hong Kong University of Science and Technology,
   hamdi@cs.ust.hk
   Daniel J. Blumenthal, University of California at Santa Barbara,
   danb@ece.ucsb.edu
   H. Jonathan Chao, Polytechnic University, chao@poly.edu
   Emilio Leonardi, Politecnico di Torino, leonardi@polito.it
   Chunming Qiao, SUNY Buffalo, qiao@computer.org
   Kenneth Yun, Applied Micro Circuits Corporation (AMCC), kyun@amcc.com