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                           Call for Papers
                         2004 BEACON Workshop

1st Workshop on Building Block Engine Architectures for COmputers and
Networks
                     http://beacon-2004.cs.ucr.edu/

                       Held along with ASPLOS-XI
                http://www.eecg.toronto.edu/asplos2004/ 
                   Park Plaza, Boston, Massachusetts

                             Oct 9-13, 2004
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Overview:
---------
Basic building block operations are data-intensive operations that are
commonly executed in network processing and server applications. Examples
include data copies (like in network processing), encryption (as in
e-commerce), compression (as in file systems), encoding (as in media
processing), parsing (as in XML-based workloads) and error detection (like
CRC in RDMA). Enabling hardware and software support for fast and efficient
processing of these basic building block operations is becoming a necessity
for future server platforms. Building block engines may be instantiated in
a number of ways in server platforms (as a CMP core, a programmable engine,
a hardware assist device, etc).

The BEACON-1 workshop will be held along with ASPLOS XI and is intended to
bring together researchers from academia and industry for an engaging
discussion on (1) the characterization of building block operations, (2) the
design, architecture and interface of building block engines and (3) the
effective use of building block engines in production servers. 

Topics of Interest (not limited to):
------------------------------------
    * Characterization of Building Block Operations 
        - Frequency, Importance, Usage, etc. 
        - Compute, Cache/Memory, I/O Requirements
    * Architectural Improvements for Building Blocks 
        - ASICs or Engines or Co-Processors
        - Micro-architectural Considerations
        - Pipelining / Parallelization 
        - Caching and Buffering
        - Stateless versus Stateful Offload
    * Programming Models and O/S Support
        - Synchronous vs. Asynchronous Execution
        - Application Interfaces and Scheduling
        - Communication and Synchronization
        - Security and Partitioning
    * Performance Analysis for Building Blocks
        - Simulation Methodologies & Tools
        - Performance Case Studies 
        - Analysis of Optimizations and Trade-offs

Paper Submission:
-----------------
We welcome submissions in the form of short papers (6 double-column pages)
or extended abstracts (5 pages). Submissions that describe early work on
server building blocks are also encouraged. Please e-mail your submissions
(preferably in pdf) to ravishankar.iyer@intel.com and
donald.newell@intel.com.
Submissions are due by August 7th. 

Workshop Chairs:
----------------
Ravi Iyer
Intel Labs
ravishankar.iyer@intel.com

Don Newell
Intel Labs
donald.newell@intel.com 

Organizing / Program Committee:
-------------------------------
Laxmi Bhuyan, UC, Riverside     
Kevin Jaffey, U. of North Carolina
Lizy John, UT, Austin
Srihari Makineni, Intel
Derek McAuley, Intel Research Cambridge
Ian Pratt, U. of Cambridge
Harrick Vin, UT, Austin
Raj Yavatkar, Intel

Important Dates:
----------------
Paper Submission:        August 7th 2004
Author Notification:     September 7th 2004
Final Paper Submission:  September 14th 2004

For More Information:
---------------------
Please visit the website or send email to ravishankar.iyer@intel.com or
donald.newell@intel.com